Dynamic vectorization in the E2 dynamic multicore architecture

PutnamAndrew,SmithAaron,BurgerDoug

Dynamic vectorization in the E2 dynamic multicore architecture

2011

PutnamAndrew
SmithAaron
BurgerDoug

Previous research has shown that Explicit Data Graph Execution (EDGE) instruction set architectures (ISA) allow for power efficient performance scaling. In this paper we describe the preliminary de...

Keywords:

Scaling
Explicit Data Graph Execution
Parallel computing
Computer science
power efficient
multicore architecture
Vectorization (mathematics)
Instruction set

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