SOPC (System on a Programmable Chip) networking based sub-microsecond level clock synchronizing method and system

The invention provides an SOPC (System on a Programmable Chip) networking based sub-microsecond level clock synchronizing method. The clock synchronizing method comprises the steps of synchronizing UTC (Universal Time Coordinated) of a remote reference primary parent clock with UTC from an external GPS (Global Positioning System) clock or a Big Dipper system clock; synchronizing each node of a local first-level PTP (Precision Time Protocol) domain with the remote reference primary parent clock through a network switching device which supports a transparent clock function; receiving an optimal primary clock from a network at the same level by each Zynq platform based slave clock which supports IEEE158V2 protocol and gigabit Ethernet for time synchronization and frequency synchronization; when a PTP domain at the next level synchronizes with the primary parent clock through a border clock, performing clock synchronization by a primary clock at the upper level; and during the period that the PTP domain at the same level masters an independent clock synchronization control right, selecting the optimal primary clock as the primary clock of the network at the same level through an optimal primary clock algorithm. The invention also provides an SOPC networking based sub-microsecond level clock synchronizing system which adopts the clock synchronizing method.