A High-perfomance Multi-format SIMD Multiplier for Digital Signal Processors

One of the most important operation in digital signal processing is multiplication. It is an underlying operation in telecommunication, photo and video processing, convolution neural networks. In order to perform these tasks, digital signal processors (DSP) must be able to execute a huge amount of multiplications and multiplication-based instructions per second. Additionally, DSP must be able to execute multiplication instructions with different data types, such as fixed point and floating point data. In this paper a high performance multi-format SIMD (single instruction, multiple data) multiplier is proposed. Proposed multiplier is based on 8×8 array of 8-bit integer multipliers, adders tree and floating point product generators, and allows to execute multiplication operations on 8-, 16-, 32- and 64-bit fixed-point data and half-, single- and double-precision floating-point data in a SIMD mode. Proposed multiplier has a wide set of multiplication-based instructions, such as multiplication with accumulation (MAC), complex multiplication, dot product, filtration and matrix multiplication, and at the same time occupy significantly smaller area in comparison with conventional multiplier unit with the same performance.