TID effects on I–V characteristics of bulk CMOS STD and ELT-based devices in 600 nm

Abstract This work presents the Total Ionizing Dose (TID) effects on the I–V characteristics of multiple standard (STD) and enclosed-layout (ELT) bulk CMOS transistors laid out in a 600 nm technology node. The devices-under-test (DUT) were irradiated to a total dose of 500 krad(Si), at a dose rate of 700 rad(Si)/h. After irradiation, the DUT were annealed at 100 °C for 168 h. The radiation-hardened (RadHard) devices and digital cells were designed employing an automated design flow methodology, presented in our previous work [1], using standard commercial processes without the need of any additional processing steps. The results indicate that the radiation tolerant cells designed with referred flow are feasible to be implement and their hardness degree is in accordance to the findings in the literature, where the transistors and circuits were designed manually. Therefore, the experimental data in this work indicate that the novel automated design flow methodology is an elegant solution to efficiently reduce time and costs for the development of RadHard devices for sensitive applications in harsh environments.