Impact of SiO 2 /Si interface micro-roughness on SILC distribution and dielectric breakdown: A comparative study with atomically flattened devices

Stress Induced Leakage Current (SILC) limits the scaling of tunnel oxide of flash memory, because it increases with the decrease of the tunnel oxide thickness. Especially, anomalously large SILC that appears on the local spots can cause bit errors. We measured Q bd and SILC characteristics of the MOSFETs with the conventional and the atomically flattened SiO 2 /Si interfaces, and the impact of the micro-roughness on Q bd and SILC has been investigated. It was found that both the numbers of the defects inducing Q bd and anomalous SILC are reduced by introducing the atomically flat SiO 2 /Si interface. And the calculated excess electric field at a projecting part is approximately 5% larger than the atomically flat part by the SILC distribution and the electric field concentration simulation. It indicates that the SiO2/Si interface micro-roughness is one of the origins that induce both the anomalous SILC and early failure in dielectric breakdown, due to localized electric field concentration effect.