Improved VLSI Architecture of Dual-CLCG for Pseudo-Random Bit Generator

In this paper, improved VLSI architecture of dual coupled linear congruential generator (CLCG) for pseudorandom bit generation is proposed to enhance the timing performance with minimum area overhead. To improve its performance, a splitting structure of the adder circuit rather than a single adder is used in linear congruential generator (LCG). Its effect on the design of a dual-CLCG is observed to compute some of the essential performance parameters such as maximum frequency of bit generation, minimum period of clock signal, initial clock latency, output to output latency and area complexity. For Spartan-3E XC500E FPGA based synthesis of proposed architecture with 8, 16 and 32-bit word length, the ISE design suite provided by Xilinx is used.