Securing More Registers with Reduced Instruction Encoding Architectures

One of the most serious constraints of an embedded system is its limited memory, which requires small code size for embedded software. One popular method to reduce the code size is reducing the instruction encoding, such as the ARM THUMB or the MIPS-16 architectures. They employ shorter instructions by reducing the field width, including those of register operands. This obviously reduces the number of registers available for register allocation than in the original architecture, which can lead to more register spills, negatively affecting the code size. This paper proposes a simple architectural upgrade by reconstructing the original register file into register banks and by providing a bank change instruction. This can allow all of the original registers to be available for register allocation when the bank change instructions are added appropriately. For such a banked register file, we propose an efficient, region-based register bank allocation technique where appropriate regions are chosen first for bank changes, followed by conventional global register allocation. As a case study, we apply the idea to the ARM THUMB architecture and evaluate how the upgrade affects its overall code size. We found that the upgrade results in an average of 5.0% code size reduction for some of MiBench and MediaBench benchmarks, compared to the original THUMB code.