Soft errors and NBTI in SiGe pMOS transistors

We have investigated single event charge collection and negative-bias instabilities in SiGe pMOSFETs that are of interest for future commercial and space applications. Single-event transient (SET) pulse polarity can depend on the location of the strike along the device channel in ways that differ from SETs in Si-based CMOS devices. The drain bias can significantly affect the total amount of collected charge and peak current values of the SETs in the tested devices. Activation energies for interface-trap buildup during negative bias-temperature stress are lower for SiGe channel pMOSFETs than for Si channel pMOSFETs. Activation energies for oxide-trap charge buildup during negative bias-temperature stress are similar for SiGe pMOSFETs and Si pMOSFETs.