Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs

Industry is facing increasingly tougher quality requirements for more complex ICs. To meet these quality requirements we need to improve the defect coverage. This paper presents a new methodology to significantly increase the defect coverage of the test patterns generated by ATPG tools. The fault model used during the ATPG is enhanced to directly target layout-based intra-cell faults. In contrast to previous techniques, such as Gate-Exhaustive, N-Detect, or Embedded-Multi-Detect, which either are too complex for real-world designs or merely improve the probability of detecting intra-cell defects, the new approach targets the actual root causes of intra-cell defects. The newly proposed Cell-Aware-methodology has been evaluated for 90nm and 65nm technologies on 1671 library cells and on 10 real industrial designs with up to 50 million faults. The experimental results show an average increase of 1.2% in defect coverage and a reduction of 420ppm in escape rate for a 50mm2 design.