A 5500FPS 85GOPS/W 3D Stacked BSI Vision Chip Based on Parallel in-Focal-Plane Acquisition and Processing

This paper presents a 2-layer 3D stacked Back Side Illuminated vision chip performing high speed programmable parallel computing by exploiting in-focal-plane pixel readout circuits. The proposed circuit exhibits a 5500fps frame rate, 5 times higher than previous works without reducing ADC resolution. It allows heterogeneous parallel computations on up to 31×31 inter-pixels neighborhoods in a single chip.