Switching well noise modeling and minimization strategy for digital circuits with a controllable threshold voltage scheme

This paper describes a new model for characterizing the switching well noise suited for application-specific integrated circuits (ASICs) of gate-array and standard-cell-style digital circuits. A new technique employed in this work is to incorporate the controllable threshold voltage scheme, necessitated by the recent demand for low power designs, into the well noise analysis. The propagation process of the noise through the well is fully analyzed, providing practical approximation and reduction techniques of the peak noise value, which are of use to estimate the possible maximum noise value at the early stage of the design. SPICE simulation results are shown to demonstrate and verify the effectiveness of these techniques in reducing the well noise and the precision of the peak approximation. A novel design methodology to optimize both area and noise is proposed based on the stochastic modeling of the multiple noise sources and their superposition effects.