Energy of CDM Failure for ICs on Package-, Wafer-and Board-Level

An energy-based failure is analyzed for Charged-Device-Model-like (CDM) discharges. The stress of an electrostatic discharge (ESD) element can be quantified and simulated, if the background capacitance of an IC domain is known. Differences between package-, wafer- and board-level are evaluated using the Capacitively Coupled Transmission Line Pulsing (CCTLP) method. The difference in the switching behavior of an ESD element due to capacitance relations is evaluated on package- and wafer-level.