Modeling device Soi mos

The present invention provides a method of modeling the SOI MOS devices, the SOI MOS device wherein the source and drain implantation is not in the end of the SOI MOS device, the method comprising: a) establishing includes an analog source and drain of the SOI MOS devices implanted in the end of the primary MOS the overall model of the device model and the junction bottom surface of the capacitance model analog source body PN junction bottom surface of the capacitance of the source body PN junction bottom surface of the capacitor model and simulate the drain body PN junction bottom surface of the capacitor leakage body PN; B) primary MOS device model of the overall model and PN junction capacitance of the source body model and the bottom surface of the drain body bottom surface of the PN junction capacitance model parameters are extracted. Modeling of the present invention provides a source-drain implantation considerations SOI MOS devices are not in the end of the bottom surface of the junction capacitance of the source body and the bottom surface of the drain bulk junction capacitance affect device performance, improve the accuracy of the model can be effectively applied to the device simulation design.