Implementation of digital IQ imbalance compensation in OFDM WLAN receivers

Although the maximum transmission speed in IEEE 802.11a WLAN is 54 Mbps, the real throughput is actually limited to 20/spl sim/30 Mbps. Except for the main effect from multi-path, we should also consider some non-ideal effects from imperfect hardware design, such as the IQ imbalance from direct conversion in RF front-end. IQ imbalance is not apparent in lower-order QAM modulation. However, in higher-order QAM modulation, it will become serious interference. In this paper, an IQ imbalance compensation circuit in IEEE802.11a baseband receiver is proposed. A low complexity time-domain compensation algorithm is used to replace the traditional high-order equalizer. MATLAB is used to simulate the whole transceiver including the channel model. After system verification, we use Verilog to implement the IQ imbalance compensation circuit with UMC 0.18 /spl mu/m CMOS 1p6m technology. Post-layout simulation results show that this scheme contributes to a very robust and easily implemented OFDM WLAN receiver.