Design of Subfield Data Aligner for Plasma Display Panels

Plasma display panel controller sends data of each subfield one by one to the panel. The signal processing block in the controller generates subfield mapped data from the frame data, which has to be arranged before sending it to the panel. The proposed design of subfield data aligner separates the data of signal processing block into different subfields and aligns it, for sending it to the panel. After aligning the data is written into SDRAM, therefore real time data writing in SDRAM with fast row switching is considered while reducing the buffer size in the aligner. When single frame data is available in the SDRAM, the data is sent to data driver buffers in the controller, for further alignment before sending it out to the panel data drivers. This paper proposes design of subfield data aligner with reduced size of buffer used for aligning purposes.