Quantum Dot Channel (QDC) Field-Effect Transistors (FETs) Using II–VI Barrier Layers

This paper describes fabrication and modeling of quantum dot channel (QDC) field-effect transistors (FETs). A QDC-FET comprises an array of thin-barrier (~1 nm) cladded Si, Ge, or other quantum dots (3 nm to 4 nm) forming an n-channel on a p-Si layer/substrate between the source and drain regions. Experimental characteristics of fabricated QDC-FETs, consisting of two layers of cladded quantum dot arrays (e.g., SiO x -cladded Si dots and GeO x -cladded Ge dots) serving as the transport channel, are presented. Unlike conventional FETs, QDC-FET structures exhibit step-like I D–V G characteristics and discretely bunched I D–V D characteristics as a function of gate voltage. The transfer characteristics appear to be similar to those of single-electron transistors (SETs). However, QDC-FETs employ transport of many electrons and operate at room temperature. A one-dimensional Tsu–Esaki equation is used to simulate the quantum dot channel and explain the steps in the current–voltage behavior. In particular, the effect of the II–VI barrier layers on Ge dots is modeled. The QDC-FET channel is also modeled as having superlattice-like mini-energy bands whose bandwidth and separation are determined by the dot size, cladding thickness, and barrier height. For a given gate voltage (which determines the carrier concentration), carriers in the inversion channel are transported via mini-energy bands that line up with the Fermi level as the drain voltage V DS is changed, producing step-like multistate electrical characteristics. Formation of the quantum dot channel enables higher-mobility transport on very low-mobility substrates or thin films such as poly-Si. The channel mobility can be further enhanced by partially removing the oxide barrier layer and replacing it with lattice-matched II–VI gate insulator layers.