Device technology limitations in monolithic switched-capacitor Σ–Δ modulators

Abstract This paper analyzes non-ideal effects and fundamental limitations encountered in Σ–Δ analog-to-digital converters realized by switched-capacitor techniques. Expressions are derived for the lower noise bound as a function of the modulator network structure. Circuit imperfections and device limitations are simulated using a behavioral model. The theoretical results are compared to simulations and actual measurements performed with monolithic implementations of the MASH and the iflf5 network structures. The circuits are implemented in a 2.0 and a 1.2 μm double-poly CMOS process, respectively.