Punch-through and DIBL Effects Exposing Nano-node SOI FinFETs under Heat Stress

Through the electrical measurement plus the heat stress to enhance the existed or latent defects of FinFETs in the nano-node process flow is a useful metrology. This method not only effectively and timely provides the mapping analysis in a whole wafer, but the sensed data may be correlated to the process variation and optimization in statistical analysis. Besides the common electrical characteristics in ON/OFF current, the punch-through and drain-induced barrier lowering (DIBL) effects like a pair of detectors are good tools to probe the channel integrity. More process parameters of VT implantation related to these two effects are discussed.