A 0.3-V 7.6-fJ/conv-step delta-sigma time-to-digital converter with a gated-free ring oscillator

An energy efficient delta-sigma time-to-digital converter (TDC) is presented in this paper. Compared with conventional circuit techniques, non-ideal effects associated with switching noise and transistor leakage can be generally prevented due to the use of a gated-free ring oscillator and leakage-suppression switches in the circuit implementation. The proposed TDC is fabricated in 90-nm CMOS, consuming a current of 5 µA from a 0.3-V supply. With first-order shaping of the quantization noise, the circuit demonstrates an equivalent number of bits (ENOB) of 10.9 bits in 50-kHz signal bandwidth.