Built-in functional tests for fast validation of a 40Gbps coherent optical receiver SoC ASIC

An SoC ASIC is an integration of many complex components such as analog cores, digital cores, user defined logic, memories, etc. If not properly planed, lab validation of such an ASIC can be time consuming. This paper proposes a design for validation architecture that includes a built-in functional test for fast lab validation and system integration. The proposed scheme has been adopted in a 40 Gbps coherent optical transmission ASIC, which consists of 20 M gates and four 20 Gsps ADCs.