Charge Trapping and Transconductance Degradation in Irradiated 3D Sequentially-Integrated FDSOI MOSFETs

Total-ionizing-dose (TID) effects are compared in 1) conventional high-temperature processed planar fully-depleted silicon-on-insulator (FD-SOI) p-channel MOSFETs, 2) 3-D sequentially integrated (3DSI) FD-SOI MOSFETs in the bottom layer with additional thermal budget and process flows due to the creation of the top layer, and 3) 3DSI low-temperature-processed FD-SOI MOSFETs in the top layer. When irradiated under worst case negative bias, 3DSI bottom-isolated transistors show significantly enhanced charge trapping and transconductance degradation than planar devices. The enhanced degradation for bottom-isolated devices is attributed primarily to increased interface- and border-trap formation at the buried oxide (BOX)/Si interface and/or lateral charge nonuniformities in the BOX. The radiation-induced transconductance degradation in top-isolated devices is attributed to the increased resistance of the portion of the channel that underlies the source/drain spacers.