A Hybrid-Loop Structure and Interleaved Noise-Shaped Quantizer for a Robust 100-MHz BW and 69-dB DR DSM

A continuous-Time delta-sigma modulator (CT-DSM) excels at high-bandwidth (BW), high-dynamic-range analog-to-digital conversion. However, CT-DSMs suffer from PVT variation, high sensitivity to timing errors, and are restricted in sampling rate. This work proposes a hybrid-loop (HL) DSM architecture to mitigate the disadvantages of CT-DSM while providing similar performance. This work also introduces a bandpass time-interleaved noise-shaping (TINS) successive-approximation (SAR) architecture, which increases the sampling rate of TINS SAR. A prototype HL-DSM with bandpass TINS-SAR quantizer is built in 28-nm CMOS and occupies a die area of 0.09 mm². The measured peak SNDR is 67.5 dB for a 100-MHz BW. The total power consumption is 13.4 mW at a sampling rate of 1.6 GS/s. The resulting Schreier FoM of 166.2 dB is comparable to state-of-the-art CT-DSM converters.