Reconfigurable Module of Multi-mode AES Cryptographic Algorithms for AP SoCs [in press]

In the implementation of the Advanced Encryption Standard (AES), as one instance of symmetrically cryptographic (crypto) algorithms, there are existing various block cipher modes used to offer higher confidentiality compared to the Electronic Codebook (ECB). In this article, we implement the AES with three different key lengths and different block cipher modes using High-Level Synthesis (HLS). The modes are Cipher Block Chaining (CBC), Cipher Feedback Mode (CFB), Output Feedback Mode (OFB), Counter (CTR), and Ciphertext Stealing (XTS) as extensions of the Electronic Codebook (ECB). All Programmable System-on-Chip (AP SoC) consisting of a hard multi-core processor and an FPGA is the target platform, and we leverage the capabilities of static and dynamic partial reconfigurations of FPGA. It is shown that the combination of a pipeline, array partitioning, and unrolled loop can lead to an increase in the data rate up to seven times. The approach comes at a trade-off of increased resource demand, which we carefully balance to achieve optimal results. Based on further evaluation, there are significant differences in throughput of the optimized CTR implementation between static and partial reconfigurations, and between the usage of Processor Configuration Access Port (PCAP) and Internal Configuration Access Port (ICAP). In the realization, the bare-metal and Linux-based Operating System implementations show a possible occurrence to implement partial reconfiguration of multi-mode AES crypto algorithms in different configurations of AP SoCs during run-time.