Novel Methodologies for Performance & Power Efficient Reconfigurable Networks-on-Chip

Emerging platform-FPGAs with embedded soft and hard processors cores can be used for system-on-chip (SoC) designs. SoC systems represent a complex interconnection of various functional elements. Existing bus based interconnect architectures do not present a scalable solution to the existing problems in the communication. Networks-on-chip (NoC) has been proposed as a new design paradigm to solve the communication bottlenecks of the bus based system design (Benini and Micheli, 2002 , Dally and Towles, 2001). The basic idea is to interconnect the various intellectual property (IP) cores using on-chip networks (Hemani et al., 2000, Dally and Towles, 2004, Duato et al. 1998). Exploiting the advantages of NoC in FPGAs for implementing SoC designs is an active area of research. Modern FPGAs can support up to 10 million gates to accommodate all logic and the associated routing. Thus, logic area is at a premium in FPGAs. In order to implement a competitive NoC architecture in FPGAs, the area occupied by the network logic should be kept to a minimum. This ensures maximum area utilization by the logic while maintaining the performance of the on-chip network. Area reduction results in increased performance and reduced power consumption of the overall system (Sethuraman et al., 2005, Sethuraman et al., 2004). Firstly an area reduction, by designing a light weight router for FPGAs, was achieved. Then, a novel router architecture designs (Multi Local Port Routers and Multi 2 Routers) that provide ample opportunity to optimize the data traffic, thereby achieving improvement in both the power and the performance were proposed. This is primarily because of the reduction in the number of packets flowing in the main networks-on-chip mesh. Also, in this research work, efficient NoC configuration generation strategies were presented