Resistive Memory Device, Resistive Memory System and Operating Method thereof

The present disclosure relates to a resistive memory system including a plurality of memory cells and resistive memory system includes a memory device that includes a resistive memory cell array; And by memory cell encodes the input data so as to correspond to the erased state and a plurality of program states which may have, but generating a write data to be written to the memory cell array, according to the write data, the memory cell having a first program state and a controller for number and a second program condition for the at least one count of the number of memory cells the erase state and the enemy to encode the input data than the at least one number of memory cells, each of the number of having different programmed state having the first program state has a highest resistance level of the state of the plurality of programs, said second program condition may have a high resistance level to a second state of the plurality of programs.