10.76 TOPS/W CNN Algorithm Circuit using Processor-In-Memory with 8T-SRAM

Implementing the CNN algorithm on-chip requires a lot of power consumption. To overcome this, research is underway to reduce power consumption by implementing certain operations of digital logic as analog circuits. The purpose of this paper is to propose a structure of new SRAM memory, and to propose CNN algorithm at the circuit level. In this study, 10.76 TOPS/W was achieved.