Frequency Division Control of Three-level APF Harmonic Based on FPGA

An active power filter (APF) harmonic current frequency division compensation digital control system is built with a Field Programmable Gate Array (FPGA) as the core processor. The FPGA has an extremely high parallel execution mode, and each harmonic calculation module can be simultaneously performed, thereby solving the problems of limited harmonic number and poor compensation effect of traditional serial execution mode. Besides, FPGA can minimize the delay caused by calculation, make the digital control system have quasi- analog circuit characteristics, and significantly improve the real- time processing. The experiments are carried out on the three- level APF prototype, and the expected experimental results are achieved. The correctness of the harmonic frequency division control method of FPGA proposed in this paper is verified.