Evaluation of performance-reliability trade-offs in a Si-Ge BiCMOS process using fast wafer level techniques

Abstract Fast wafer-level reliability (fWLR) techniques are successfully implemented in order to investigate several gate oxide reliability–performance tradeoffs that affect the architecture of a high speed BiCMOS process. Fast feedback of device and reliability parameters is required during process development in order to avoid failures during process qualification. This study highlights some performance–reliability tradeoffs that had to be overcome during the development of a modern BiCMOS process.