Dielectric-semiconductor interface for high-k gate dielectrics for sub-16nm CMOS technology

Scaling for sub-16 nm CMOS technology requires EOT scaling of gate dielectric beyond 0.7 nm. Various atomic layer deposition (ALD) methods of HfO 2 -based high-k gate dielectrics are currently underway to enhance the dielectric constant and reliability in order to meet the above requirements. In this work we evaluated the interface of samples with cyclic deposition of ALD Hf 1−x Zr x O 2 where the dielectrics were exposed to intermediate slot plane antenna (SPA) Ar plasma (DSDS) or annealing (DADA). Zr addition in HfO 2 seems to modify the charge state of the oxygen vacancy formation. The cyclic SPA plasma exposure further reduces the oxygen vacancy formation because of the film densification. We also studied the High-k/Si interface by varying the Al percentage and distribution in HfO 2 when HfAlO x and HfO 2 are deposited by ALD in a multi-layered structure. Presence of excess Al in the interfacial layer moderately increased the interface state density. It is because of the structure of hafnium aluminum oxide film. Devices with less than 2% Al/(Hf+Al)% showed a resistance to stress. When high-k dielectrics are deposited on high-mobility substrates like Ge and III-V materials the electrical performance in these devices depends on the high-k deposition process, precise selection of deposition parameters, predeposition surface treatments and subsequent annealing temperatures. This work outlines some of the recent developments of EOT scaling of high-k gate dielectrics on Ge and how it impacts the interface.