Gate-Exhaustive and Cell-Aware pattern sets for industrial designs

Industry is facing very high quality requirements for today's and tomorrow's ICs. Especially in the automotive market these quality requirements need to be fulfilled. To achieve this, we need to improve currently used test methods and fault models to improve the overall defect coverage. This paper presents achieved results from 1500 CMOS 65nm library cells and from 10 industrial designs applying Gate-Exhaustive and defect oriented Cell-Aware pattern sets.