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Data-line wiring delay reduction techniques for high-speed BiCMOS SRAM's
Data-line wiring delay reduction techniques for high-speed BiCMOS SRAM's
1991
Yukihiro Urakawa
M. Matsui
A. Suzuki
H. Kato
T. Hamano
Kazuyuki Sato
T. Ohtani
Kiyofumi Ochii
Keywords:
Electronic engineering
Bipolar junction transistor
Computer science
BiCMOS
Static random-access memory
Embedded system
ultra large scale integration
random access memory
data lines
bicmos integrated circuits
Electrical engineering
Correction
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