A clock and data recovery circuit with wide linear range frequency detector

As the data rate increases above Gb/s, the design of a clock and data recovery (CDR) circuit becomes a great challenge. A 3.125-Gb/s CDR is proposed to shorten the frequency acquisition time by employing a wide-linear-range frequency detector. Fabricated in a 0.18-mum 1P6M CMOS technology, the output jitter of this proposed CDR is measured as 70 ps (peak-to-peak) and 8.3 ps (rms). The measured bit-error rate (BER) is less than 10 -12 for 2 31 -1 PRBS. The proposed CDR occupies a chip area of 0.61 mm times 0.61 mm and dissipates 61 mW from a single 1.8-V power supply.