CNFET을 사용한 6T SRAM 설계 및 성능 분석

Carbon Nanotube Field-Effect Transistor (CNFET) is known to shows approximately a tenfold superior Energy Delay Product (EDP) than that of CMOS transistor. This paper presents the design of CNFET based 6T SRAM and compares its performance with conventional CMOS based 6T SRAM cell. CNFET based 6T SRAM cell is optimized in terms of Static Noise Margin (SNM). Simulation results show CNFET based SRAM cell has about 15 and 50 percent higher hold and read SNM than that of CMOS based SRAM cell.