Application results of lot-to-lot high-order overlay correction for sub-60-nm memory device fabrication

According to the international technology roadmap for semiconductors 2007 overlay error should be controlled under 12 nm for sub-60-nm memory devices. To meet such a tight requirement, lot-to-lot high order overlay correction (HOC) is evaluated for the gate and contact layers of dynamic random access memory. A commercial package of HOC is available from scanner makers such as ASML, Canon, and Nikon. Note that only wafer corrections are investigated for this particular experiment. Reticle corrections are excluded. Experimental results verify 1 to 3 nm of overlay improvement by applying HOC. However, the amount of improvement is layer (process) dependent. It turned out that HOC is not an overall solution. It should be applied carefully for a certain process conditions. Detailed experimental results are discussed.