Packaging method of improving antistatic capability of integrated circuit chip

The invention discloses a packaging method of improving the antistatic capability of an integrated circuit chip. The method comprises the steps: producing a power cord loop and a ground cord loop on a packaging tube shell; connecting one or a plurality of capacitors and a resistor between the power cord loop and the ground cord loop; leading one or a plurality of positions of the integrated circuit chip, which are connected with a power cord inside the chip to the power cord loop; and leading one or a plurality of positions of the integrated circuit chip, which are connected with a ground cord inside the chip to the ground cord loop. The invention enables chips with poor electrostatic discharge (ESD) protection capability inside the integrated circuit chip to reach good ESD protection capability after packaging.