High Speed radix256 algorithm using parallel prefix adder

A finite impulse response (FIR) filter computes its output using multiply and accumulate operations. In the present work, a FIR filter based on novel higher radix-256 and RB arithmetic is implemented. The use of radix-256 booth encoding reduces the number of partial product rows in any multiplication by 8 fold. In the present work inputs and coefficients are considered of 16-bit. Hence, only two partial product rows are obtained in RB form for each input and coefficient multiplications. These two partial product rows are added using carry free RB addition. Finally the RB output is converted back to natural binary (NB) form using RB to NB converter. The performance of proposed multiplier architecture for FIR filter is compared with computation sharing multiplier (CSHM)