A monolithic low-bandwidth jitter-cleaning PLL with hitless switching for SONET/SDH clock generation

A single-chip jitter-cleaning PLL with hitless switching is presented. By utilizing the mostly-digital phase build-out technique, the steady-state output phase step after switching is bounded within 200ps. At the loop bandwidth of 800Hz, the maximum output phase transient slope is 2 chip is fabricated in a 0.25mum standard CMOS process and consumes 350mW at 3.3V