A Novel Low Power High Speed BEC for 2GHz Sampling Rate Flash ADC in 45nm Technology

This paper depicts the idea of a novel bubbleerror corrector for removing the bubble error of order 1and consuming less power. The earlier bubble error corrector(BEC) needed large number of transistors thus requiring morepower. 3-input NAND gate with two inverted inputs is also usedas a BEC but it requires more power than the proposed one asit requires more number of transistors. With a supply of 1Vin 45nm technology, the BEC consumes 4.14 pico-Watt of dcpower and 9.62 micro-Watt of average power. The maximumdelay is calculated to be 20 pico-seconds. When used with Fattree encoder it consumes 0.3 nano-Watt of dc power and 27.34micro-Watt of average power and has a maximum delay of 74.76 pico-seconds.