A Polyphase Decimation Filter for Time-Interleaved ADCs in Direct-RF Sampling Receivers

Decimation filters in direct-RF sampling receivers are implemented with the polyphase decompositions of cascaded integrator-comb (CIC) filters to decrease gigasamples per second (GS/s) rates to low ones. First delays and decimators of the first decimation filter in the receiver can be eliminated in a time-interleaved ADC (TI-ADC) with the same number of channels as a decimation factor of the filter. However, the remaining adders need to operate at the same rate as each ADC samples (>1 GS/s), limiting the maximum operating speed of the receiver. We present a polyphase filter with a decimation factor of twice the channel number. This enables decimators to be inserted before the adders, reducing their operating frequencies to a half of the sampling frequency of each ADC. We synthesize a 7-bit polyphase filter based on a 2nd-order CIC filter with a decimation factor of 8 for a 4-channel TI-ADC by using a 65-nm CMOS process. Simulations show that the filter combined with I/Q mixers operates at twice the operating frequency (1.67 GS/s) of the conventional one with 2.0 mW, while consuming twice or more the chip area.