Design of 0.18μm CMOS Programmable Frequency Divider Based on Standard Cells

The design of a programmable frequency divider, which is one of the components of the phase-locked loop (PLL) frequency synthesizer for transmitter and receiver in IEEE 802.11a standard, is investigated. The main steps in very large-scale integration (VLSI) design flow such as logic synthesis, floorplan and placement & routing (P & R) are introduced. By back-annotating the back-end information to the front-end design, the custom wire-load model is created and used for optimizing the design flow under deep submicron technology. The programmable frequency divider is implemented based on Artisan TSMC (Taiwan Semicoductor Manufacturing Co. Ltd.) 0.18 μm CMOS (complementary metal-oxide-semiconductor) standard cells arid fabricated. The chip area is 1360.5 μm^2 and can work in the range of 100 to 200 MHz. The measurement results indicate that the design conforms to the frequency division precision.