Model-Based Fault Injection for Failure Effect Analysis

Abstract —We propose a fault-injection system (FIS) that can inject faults such as read/write margin failures and soft errors into a SRAM environment. The fault case generator (FCG) generates time-series SRAM failures in 7T/14T or 6T SRAM, and the proposed device model and fault-injection flow are applicable for system-level verification. For evaluation, an abnormal termination rate in vehicle engine control was adopted. We confirmed that the vehicle engine control system with the 7T/14T SRAM improves system-level dependability compared with the conventional 6T SRAM. Keywords- fault injection; SRAM; system-level verification; dependable processor I. I NTRODUCTION Recently, VLSI is increasingly becoming a key part in various industrial products. Therefore, its reliability is important. However, a transistor is more vulnerable and sensitive to soft errors and negative bias temperature instability (NBTI) because the process technology is scaled down. In addition, increasing variability in the transistor worsens its reliability and LSI yield. On the LSI, SRAM is comprised of the smallest-size transistors, which is thus the dominant factor that determines the LSI’s reliability. Accordingly, high reliability is required for SRAM on the system LSI [13]. There have been many studies and implementations of fault injection into the LSI [46]. These studies injected stuck-at faults and transient faults due to single event upsets (SEUs) and supply voltage fluctuations. However, these fault-injection schemes do not consider the physical characteristics of the vulnerable SRAM. In addition, they cannot perform large-scale verification considering a large number of physical LSIs each with different characteristics due to the random process variation. II. F