Low Power Digital PWM Buck Converter With a Clock-Gating Shift-Register

This paper proposes a low power digital PWM buck converter with a clock-gating shift-register. The digital PWM controller of the digital buck converter adjusts the PWM duty ratio using a fast shift-register and a slow bidirectional shift-register. The fast shift-register consumes a large clock power, because the bit-width and clock frequency of the shift-register increase in proportion to the PWM duty ratio resolution. The proposed clock-gating shift-register reduces the clock power by supplying the clock signal to only D flip-flops (DFFs) used to generate the PWM signal in the shift-register. It saves 22% of the clock power when the PWM duty ratio is 50% at the continuous conduction mode. And it saves 22%-93% when the PWM duty ratio is 10%-50% at the discontinuous conduction mode. The digital PWM buck converter was designed using a 65nm CMOS process. It supplies the load current of 0.5mA-10mA when the supply voltage is 0.6V and output voltage of 0.1V-0.5V.