Dedicated VLSI Architecture for 3-D Discrete Wavelet Transform

This Paper Presents an architecture of the lifting based 3-d discrete wavelet transform (DWT), which is a powerful image and video compression algorithm. With 3-D-DWT architectures the memory requirement, block based or scan-based architectures with independent group of pictures (GOP) transform have been reported. However, blocking degrades the PSNR quality while the independent GOPs introduce annoying jerks in video playback due to PSNR drop at transform boundaries. The proposed design is one of the first lifting based complete 3-D-DWT architectures without group of pictures restriction. The new computing technique based on analysis of lifting signal flow graph minimizes the storage requirement. This architecture enjoys reduced memory referencing and related low power consumption, low latency, and high throughput compared to those of earlier reported works. The adders from the library and device dual port block RAMs have been utilized as the principal resources for the designed processor. Simulation is performed by ModelSim XE III 6.0a, which yields a set of end results completely.  The Proposed Architecture has been has been successfully implemented and synthesized on Xilinx 14.2 ISE  Design Suite.