A 9.4MHz-to-2.4GHz Jitter-Power Reconfigurable Fractional-N Ring PLL for Multi-Standard Applications in 7nm FinFET CMOS Technology

This paper proposes a ring-VCO-based fractional-N PLL with a noise-power reconfigurable ring-VCO and a self-chopped reference frequency doubler for multi-standard applications. To cover the various specifications of SoC chips, the jitter and power of the proposed PLL can be reconfigurable through R and C adjustments of the ring-VCO. Moreover, the reference frequency doubler provides 6 dB improvements on DSM quantization noise without reference spurs. In addition, the PLL also guarantees a wide frequency range from 9.4 MHz to 2.4 GHz while maintaining optimum loop-bandwidth against process, voltage, and temperature variations through an adaptive loop-bandwidth technique. The measured integrated RMS-jitter and power consumption of this PLL are 6.2 ps and 6 mW, respectively for the low-jitter specification, which translated to -216.4 dB FoM, and 13 ps and 2.1 mW, respectively for the low-power specification, which achieves 0.85 mW/GHz efficiency.