Electrical characteristics and contact resistance of B + -and BF 2 + -implanted silicon diodes with furnace and rapid thermal annealing

Shallow p + -n junctions in silicon are fabricated by the implantation of 10 keV B + or 50 keV BF 2+ ions at a fluence of 3 × 10 15 / cm 2 through a capping layer of 25-nm SiO 2 . Sheet resistance, contact resistivity, and forward and reverse bias leakage current are measured for various furnace and rapid thermal annealing (RTA) conditions. SIMS profiles are included. RTA allows the simultaneous achievement of junctions with j 2 , R_{s}\simeq 50 \Omega/ , and \rho_{c}\simeq 2 \times 10^{-6}\Omega . cm 2 for junction depths of the order of 0.25 µm as mesured by the traditional bevel-and-strain method.