Improvement of the RF power performance of nLDMOSFETs on bulk and SOI substrates with ‘ribbon’ gate and source contacts layouts

This paper presents the RF power performances of nLDMOSFETs fabricated on bulk and SOI substrates and the layout changes made to improve these performances. It is shown that simple design rules modifications can be done to increase f max , by reducing the gate resistance, without penalizing f T . A significant improvement of both the output power P out and the power added efficiency PAE is demonstrated in A and AB classes.