Crosspoint Memory Arrays: Principle, Strengths and Challenges

This paper presents an outlook of crosspoint memory arrays. We survey the characteristics, strengths and challenges of crosspoint array composed by a resistive memory device integrated in series with a back-end selector. We present the performances of our 1S1R technology composed of an HfO 2 OxRAM (1R) combined with a GeSeSbN based Ovonic Threshold Switch (1S). We benchmark our results with a detailed collection of experimental data reported in the literature.