Modeling of submicronic TMOS

We have developed a model of TMOS submicronic with ultra thin oxide layers as small as 4,5-nm in order to study MOSFET's output characteristics and its associated characterization facility for advanced integrated-circuit design are described. This model makes use of the SPICE3F4 simulator and takes in consideration the majority of the physical effects describing the device's real behavior. The validation of our model has provided us with results on the drain current I DS versus drain voltage V DS . Our analysis and conclusions should be of interest to all who work with VLSI circuit technology.