Hardware architecture for real-time EEG-based functional brain connectivity parameter extraction

In this work, we proposed a novel architecture for real-time quantitative characterization of functional brain connectivity networks derived from Electroencephalogram (EEG). It consists of two main parts - calculation of Phase Lag Index (PLI) to form the functional connectivity networks and the extraction of a set of graph-theoretic parameters to quantitatively characterize these networks. The architecture was developed for a 19-channel EEG system. The system can calculate all the functional connectivity parameters in a total time of 131µs, utilizes 71% logic resources, and shows 51.84 mW dynamic power consumption at 22.16 MHz operation frequency when implemented in a Stratix IV EP4SGX230K FPGA. Our analysis also showed that the system occupies an area equivalent to approximately 937K 2-input NAND gates, with an estimated power consumption of 39.3 mW at 0.9 V supply using a 90 nm CMOS Application Specific Integrated Circuit (ASIC) technology.