A Hierarchical Track and Hold Circuit for High Speed ADC-Based Receivers in 22nm FDSOI

A Hierarchical Time-Interleaved (TI) track and hold (T&H) circuit for ultra high speed ADC-based wireline receivers is presented. The circuit is designed as a front-end of a 7-bit 56 GS/s 64-way TI ADC. It consists of three T&H stages of demultiplexing sampled at 28GHz, 3.5 GHz and 875 MHz, respectively. The overall SNR is limited by the sampling capacitors, which are sized to meet the link budget. The T&H stages were designed in 22 nm FDSOI while consuming 90.1 mW.